1. Field of the Invention
The present invention relates to memory circuitry, and, more particularly, to static read circuitry and a method of reading memory in the context of static read circuitry.
2. Related Art
A register-file is a type of memory used in computer systems. Register files are commonly used for storing information related to execution of a computer program, such as, for example, a result of adding or multiplying. It is conventional that architected registers of a processor are implemented as register files. A static register-file bit-read circuit 100 is shown in FIG. 1A, according to the prior art. The circuit 100 is for reading a binary value that is held in a selected one of eight, one-bit wide register-file cells, as are known in the prior art. Such a register-file cell 124 is operable for holding a binary bit value.
Referring now to FIG. 1E, details are shown for a typical prior art register-file cell 124. Cell 124 includes a memory latch formed by a pair of crossed coupled inverters I1 and I2, one node of which is coupled to an output inverter I3 that has its output coupled to the cell's corresponding selector 122 (FIG. 1C, see also FIG. 1A). The other node of the I1/I2 latch is coupled to a conducting electrode of an NFET Q6. The other conducting electrode of Q6 is for writing data to the I1/I2 latch via the WR_DATA line. The input of inverter 13 is also coupled to a conducting electrode of an NFET Q5. The other conducting electrode of Q5 is for writing the complement of the data to the I1/I2 latch via the WR_DATA_N line. The gates of Q5 and Q6 are coupled to a write word line, WR_WL.
Referring again to FIG. 1A, the eight-cell register-file bit-read circuit 100 includes a decoder 110, a multiplexer 120 and an output inverter 130. The decoder 110 receives three address-bit signals A0, A1 and A2. A typical decoder 110 is shown in FIG. 1B and described further herein below. Responsive to the state of the three address signals, decoder 110 asserts a select signal on one of its eight output select lines, SEL_0, SEL_1, SEL_2, etc. through SEL_7. Each select line corresponds to one of the register-file cells 124 (FIG. 1E).
Referring now to FIG. 1B, details are shown for decoder 110, according to the prior art. The decoder 110 has eight, three-input AND gates, AND_0 through AND_7, having their outputs coupled to respective select lines, SEL_0 through SEL_7. The decoder 110 also has three inverters 17, 14 and 16 having their inputs coupled to respective address-bit lines A0, A1 and A2. AND gate AND_0, for example, has its three inputs coupled to the outputs of the three inverters, i.e., A0_N, A1_N and A2_N on its respective inputs, so that AND_0 drives its SEL_0 output high in response to all of the address bit signals being low. Similarly, each of the other AND gates is coupled to a combination of the address-bit signals or their complements, as shown in FIG. 1B such that a different one of the select lines is driven high for each one of the eight combinations of address bits. A logic table is set out below for this function.
A0A1A2SEL_0SEL_1SEL_2SEL_3SEL_4SEL_5SEL_6SEL_70001000000000101000000010001000000110001000010000001000101000001001100000001011100000001
Referring again to FIG. 1A, the eight select lines of decoder 110 are coupled to multiplexer 120. Specifically, multiplexer 120 includes eight selectors 122, as are known in the prior art.
Referring now to FIG. 1C, details are shown for a typical selector 122, according to the prior art. The selector 122 has an NFET/PFET pair of transistors N_0 and P_0 that form a transmission gate having one of their sets of conducting electrodes coupled to the output node of the multiplexer RD_DATA and the other one of their sets of conducting electrodes coupled by a RD_DATA line to the selector's corresponding register-file cell 124 (FIG. 1E, see also FIG. 1A). The gate of N_0 is coupled to the selector's input, which in the case of the first, i.e., topmost, selector 122 shown in FIG. 1A is select line SEL_0. The gate of P_0 is also coupled to the selector's input, but through an interposing inverter 10. The input is coupled (via the select line SEL_0 in the case of the first selector 122) to decoder 110 (FIG. 1B, see also FIG. 1A).
Referring again to FIG. 1A, each one of the selectors 122 in register-file bit-read circuit 100 is coupled to a respective one of the register-file cells 124 and that cell's respective one of the eight output select lines, SEL_0, SEL_1, SEL_2, etc. through SEL_7. The multiplexer 120 is operable for its selectors 122 to conductively couple one of the register-file cells 124 to the output inverter 130 responsive to the select signal asserted by the decoder 110 on the cell's corresponding select line so that the binary bit value of the selected cell drives the multiplexer output node and thereby drives the inverter 130 input. Thus, the binary value held in the selected register-files cell may be read on inverter 130 output line, READ_DATA.
In certain applications data cannot be read fast enough from register-file cells 124 using circuit 100. A big contributing factor to the speed limitation is output capacitance of the multiplexer 120, since the multiplexer's output node has diffusion and wire capacitance of eight n-channel and eight p-channel devices in parallel, i.e., in the selectors 122 (FIG. 1C), as well as gate capacitance of inverter 130. Thus, multiplexer 120 has relatively long rise and fall times, which degrades performance.
A faster register-file bit-read circuit 200 is shown in FIG. 2, according to the prior art. Circuit 200 also includes a decoder 210 coupled to a multiplexer 220, which in turn is coupled to an output gate 230, which in this case is a NAND gate.
One factor that improves the speed of circuit 200 is an improvement in output capacitance for multiplexer 220. The selectors 222 for multiplexer 220 are grouped into two groups of four parallel selectors in each group, with each group being coupled to a different output node READ_DATA_1 and READ_DATA_2, which in turn is coupled to a different input of NAND gate 230. Thus, the capacitance is reduced on each of the connections to output gate 230.
Another factor that improves the speed of circuit 200 is that the circuit 200 is a dynamic circuit. That is, it operates responsive to a cyclical timing signal. In particular, its multiplexer 220 output nodes are precharged every clock cycle responsive to the cyclical timing signal, CLOCK. Accordingly, multiplexer 220 also includes two prechargers, PRECHARGER_1 and PRECHARGER_2, coupled to its respective output nodes READ_DATA_1 and READ_DATA_2. Responsive to the CLOCK signal going low these prechargers drive their respective nodes to VDD during a precharge interval every clock cycle.
Referring now to FIG. 1D, a typical selector 222 is illustrated according to prior art. Note that output nodes READ_DATA_1 and READ_DATA_2 are precharged high before read operations. Since none of the selectors 222 of FIG. 2 have to drive their output nodes high, each selector 222 of FIG. 1D omits the PFET and inverter shown for the typical selector 122 of FIG. 1C. That is, a PFET is mainly needed in order to pass a high signal, so it is not needed in the case of dynamic circuit 200.
The decoder 210 of circuit 200 is like the decoder 110 shown in FIG. 1B except that in decoder 210 the AND gates that drive the select lines each has an additional input that receives a control signal, ENABLE. The ENABLE signal is low when the CLOCK signal is low. The AND gates deassert their SELECT signals when the ENABLE signal is low. This prevents possible short circuits through the selectors 122 during precharging, when the CLOCK signal is low and output nodes READ_DATA_1 and READ_DATA_2 are driven high.
While circuit 200 is faster, nevertheless it has some drawbacks. It needs to be clocked and a timed ENABLE signal needs to be available, which increases design complexity and clock loading. In turn, this increases energy consumption. Therefore, a need exists for an improved register-file bit-read method and apparatus.